1. general description the 74ahc164-q100; 74ahct164-q100 shift register is a high-speed si-gate cmos device and is pin compatible with low-powe r schottky ttl (lsttl). it is specified in compliance with jedec standard no. 7a. the 74ahc164-q100; 74ahct164-q 100 input signals are 8-bit serial through one of two inputs (dsa or dsb). either input can be us ed as an active high enable for data entry through the other input. both inputs must be connected together or an unused input must be tied high. data shifts one place to the right on each low-to-high transition of the clock input (cp). it enters into output q0, which is a logica l and of the two data inputs (dsa and dsb). these data inputs existed one set-up time, prior to the rising clock edge. a low-level on the master reset (mr ) input overrides all other inputs and clears the register asynchronously, forcing all outputs low. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger actions ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc164-q100: cmos level ? for 74ahct164-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74ahc164-q100; 74ahct164-q100 8-bit serial-in/parallel-out shift register rev. 1 ? 5 july 2013 product data sheet
74ahc_ahct164_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 5 july 2013 2 of 19 nxp semiconductors 74ahc164-q100; 74ahct164-q100 8-bit serial-in/parallel-out shift register 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc164-q100 74AHC164D-Q100 ? 40 ? c to +125 ? c so14 plastic small outl ine package; 14 leads; body width 3.9 mm sot108-1 74ahc164pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahc164bq-q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74ahct164-q100 74ahct164d-q100 ? 40 ? c to +125 ? c so14 plastic small outl ine package; 14 leads; body width 3.9 mm sot108-1 74ahct164pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahct164bq-q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 fig 1. functional diagram 001aac425 1 2 31 01 3 6 41 2 51 1 8 9 q0 q1 q2 8-bit serial?in/parallel?out shift register q3 q4 q5 q6 q7 dsb cp mr dsa
74ahc_ahct164_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 5 july 2013 3 of 19 nxp semiconductors 74ahc164-q100; 74ahct164-q100 8-bit serial-in/parallel-out shift register fig 2. logic symbol fig 3. iec logic symbol 001aac423 3 1 2 4 5 6 10 11 12 13 8 9 q0 q1 q2 q3 q4 q5 q6 q7 cp dsb dsa mr 001aac424 9 8 & 3 1 2 4 5 6 10 11 13 12 r c1/ 1d srg8 fig 4. logic diagram 001aac616 q0 d ff1 q cp r d cp dsb dsa mr q1 d ff2 q cp r d q2 d ff3 q cp r d q3 d ff4 q cp r d q4 d ff5 q cp r d q5 d ff6 q cp r d q6 d ff7 q cp r d q7 d ff8 q cp r d
74ahc_ahct164_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 5 july 2013 4 of 19 nxp semiconductors 74ahc164-q100; 74ahct164-q100 8-bit serial-in/parallel-out shift register 5. pinning information 5.1 pinning 5.2 pin description (1) the die substrate is attached to this pad using conductive die attach mate rial. it cannot be used as a supply pin or input. fig 5. pin configuration so14 and tssop14 fig 6. pin configuration dhvqfn14 $ + & |